Design for Test of Asynchronous Networks on Chip (NoCs)

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Design for Test of Asynchronous Networks on Chip
Design for Test of Asynchronous Networks on Chip
 Tạp chí Proceedings of the 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems 2006 May 18-21; 00 ():163-167
 Tác giả   Xuan-Tu TRAN, Vincent BEROULLE, Jean DURUPT, Chantal ROBACH, and François BERTRAND
 Nơi thực hiện   Prague, Czech Republic
 Từ khóa   Design for Test (DFT), Network on Chip (NoC), Testability
  DOI   URL  [ PDF]



Thanks to many advantages, asynchronous circuits have been used to solve the interconnect problems faced by system-on-chip (SoC) designers. Some asynchronous Networks-on-Chip (NoCs) architectures are proposed for the communication within SoCs, but lack of methodology and support for manufacture testing to ensure these communication architectures work correctly. In this paper, we present an innovative asynchronous DFT architecture that allows testing the asynchronous communication network architectures, as well as the synchronous computing resources and the asynchronous/synchronous network interfaces on the asynchronous NoC-based SoCs. This asynchronous DFT architecture is implemented in Quasi Delay Insensitive (QDI) asynchronous circuits and uses an area of about 20*8 Kgates in an asynchronous NoC-based SoC of 4.5 Mgates without memories.

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