How to Implement an Asynchronous Test Wrapper for Networks-on-Chip Nodes
| How to Implement an Asynchronous Test Wrapper for Networks-on-Chip Nodes | |
| How to Implement an Asynchronous Test Wrapper for Networks-on-Chip Nodes | |
| Tạp chí The 12th IEEE European Test Symposium (ETS 2007) 2007 May 20-24; 00 (): | |
| Tác giả | Xuan-Tu Tran, Jean Durupt, François Bertrans, Vincent Beroulle, and Chantal Robach |
| Nơi thực hiện | Freiburg, Germany |
| Từ khóa | Design for Test (DfT), Network on Chip (NoC), Testability, GALS, Systems-on-Chip Testing |
| DOI URL [ PDF] | |
English[sửa]
Abstract[sửa]
The Network-on-Chip (NoC) paradigm is currently known as an alternative solution for the on chip communication in the next SoC generation, especially, asynchronous NoCs. One of the challenges for asynchronous NoC-based systems design is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high-speed Test Access Mechanism (TAM). This architecture is designed to test all network elements (routers, communication channels), but it can also be used to test computational resources. In this paper, we introduce how to realize and implement the test wrapper in Quasi Delay Insensitive (QDI) asynchronous logic style. The validation and experimental results are also presented.
Citation:[sửa]
Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach, "How to Implement an Asynchronous Test Wrapper for Networks-on-Chip Nodes," The 12th IEEE European Test Symposium (ETS), 2007.
