Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip
| Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip | |
| Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip | |
| Tạp chí Proceedings of the 1st ACM/IEEE Symposium on Networks-on-Chips (NOCS 2007) 2007 May 6-9; 00 (): | |
| Tác giả | Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrans, Vincent Beroulle, and Chantal Robach |
| Nơi thực hiện | Princeton, NJ, USA |
| Từ khóa | Design for Test (DfT), Network on Chip (NoC), Testability, GALS, Systems-on-Chip Testing |
| DOI URL [ PDF] | |
English[sửa]
Abstract[sửa]
The Networks on Chip (NoCs) paradigm has recently emerged as an alternative solution for large complex SoCs' communication. Despite having many attractive attributes, NoCs design has also lots of challenges. One of the challenges is testing network architectures (routers and communication channels) for manufacturing defects, especially, the test of asynchronous NoCs. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable fully asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high throughput Test Access Mechanism (TAM). This paper presents the realization and implementation of this DfT architecture. The validation and experimental results are also presented.
Citation:[sửa]
Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach, "Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip," The 1st ACM/IEEE Symposium on Networks-on-Chips (NOCS), 2007.
